Field of the Invention
The present invention relates to a semiconductor device in which TFTs are formed in layers stacked on a substrate.
Description of Related Art
Semiconductor devices of recent years have employed a stacked-type memory cell array having a multilayer structure on a substrate in order to deal with an increase in capacity and a reduction in size. Attention has been focused on a technique for forming a transistor in such a memory cell array, in which semiconductor material capable of being stacked in a low temperature process such as polysilicon or oxide semiconductor is used to form a channel. For example, a structure has been proposed which includes a transistor in which the polysilicon is used as the channel in a stacked-type NAND flush memory (for example, see Non-Patent References 1 to 6). Further, for example, a structure has been proposed in which a stacked-type DRAM, NAND flush memory, or ReRAM/PCRAM is formed by attaching monocrystalline silicon layers to one another and stacking them (see Non-Patent References 7 to 9).    [Non-Patent Reference 1] Ryota Katsumata, et al. “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices” Symposium on VLSI Technology Digest of Technical Papers, pp. 136-137 (2009).    [Non-Patent Reference 2] Jiyoung Kim, et al. “Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)” Symposium on VLSI Technology Digest of Technical Papers, pp. 186-187 (2009).    [Non-Patent Reference 3] Wonjoo Kim, et al. “Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage” Symposium on VLSI Technology Digest of Technical Papers, pp. 188-189 (2009).    [Non-Patent Reference 4] Jaehoon Jang, et al. “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory” Symposium on VLSI Technology Digest of Technical Papers, pp. 192-193 (2009).    [Non-Patent Reference 5] Hang-Ting Lue, et al. “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 131-132 (2010).    [Non-Patent Reference 6] Sungj in Whang, et al. “Novel 3-Dimensional Dual Control-Gate with Surrounding Floating-Gate (DC-SF) NAND Flash Cell for 1Tb File Storage Application” IEEE IEDM10-668-671, pp. 29.7.1-29.7.4 (2010).    [Non-Patent Reference 7] Monolithic 3D, Inc. Technology Breakthrough, Monolithic 3D DRAM    [Non-Patent Reference 8] Monolithic 3D, Inc. Technology Breakthrough, Monolithic 3D NAND Flash Memory    [Non-Patent Reference 9] Monolithic 3D, Inc. Technology Breakthrough, Monolithic 3D Non-Volatile Memory: RRAM, PCM
When applying the above conventional techniques to a memory, it is difficult to ensure a high-speed operation. That is, in the structure disclosed in the above Non-Patent References 1 to 6, the polysilicon in which carrier mobility is smaller compared with monocrystal channel is used as the channel of a transistor, which reduces its conductance. Therefore, on-current of the transistor becomes small and the high-speed operation is hindered. Further, in the technique disclosed in the above Non-Patent References 7 to 9, a process needs to be added when manufacturing a semiconductor memory, in which a monocrystalline silicon wafer having an oxide film and ion-implanted with hydrogen is formed into a thin film and the film, is stacked, thereby increasing manufacturing cost.